Scalability of a second generation Z-RAM cell: A computational study

Advanced f oating body Z-RAM memory cells are studied and in particular, their scalability is investigated. First, a Z-RAM cell based on a 50nm gate length double-gate structure corresponding to state of the art technology is studied. A bi-stable behavior essential for Z-RAM operation is observed even in fully depleted structures. It is demonstrated that by adjusting the supply source-drain and gate voltages the programming window can be adjusted. The programming window is appropriately large in voltage as well as in current. We further extend our study to a Z-RAM cell based on an ultra-scaled double-gate MOSFET with 12.5nm gate length. We demonstrate that the cell preserves its functionality by providing a wide voltage operating window with large current differences. An appropriate operating window is still observed at approximately 25-30% reduced supply voltage, which is an additional benef t of scaling. The relation of the obtained supply voltage to the one anticipated in an ultimate MOSFET with quasi-ballistic transport is discussed.